9900 Cache Bus Computer Port Adapter

User’s Guide

PB9920-9001-02

La ; C Maevsrey INDUSTRIES wien 9505 OS

E1984 by System Industries

WARNING

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used in accordance with the instructions manual, may cause in- terference to radio communications. As temporarily permitted by regulation, it has not been tested for compliance with the limits for Class A computing devices pursuant to Subpart J of Part 15 of FCC Rules, which are designed to provide reasonable pro- tection against such interference. Operation of this equipment in a residential area is likely to cause interference in which case, the user, at his own expense, will be re- quired to take whatever measures may be required to correct the interference.

Proprietary Statement

System Industries has prepared this manual for use by System Industries personnel, licensees, and customers. The information contained herein is the property of System Industries and shall neither be reproduced in whole nor in part without prior written approval from System Industries.

System Industries reserves the right to make changes, without notice, to the specifica- tions and materials contained herein, and shall not be responsible for any damages (including consequential) caused by reliance on the material as presented, including, but not limited to, typographical, arithmetic, and listing errors.

PB9920-9001-02

/

LIMITED WARRANTY

Disk Controller. System Industries warrants that its products are free from defects in materials and workman- ship and meet System Industries’ performance specifications. The warranty period is ninety (90) days from the date of shipment to Buyer. This warranty is limited by the paragraphs below.

Return to Factory. If Buyer discovers a defect in a System Industries product covered by this agreement, Buyer's exclusive remedy is to ship the product back to System Industries’ factory where System Industries will, at its option, either repair or replace the product. This remedy applies if System industries receives the returned product on or before the tenth day after the expiration of the warranty period and Buyer notifies System industries of the defect before returning the product.

Cost to Buyer of Repairs or Replacement. Buyer must prepay freight charges to System Industries. System Industries will pay return freight to Buyer. There is no other charge for repair or replacement during the warranty period.

Transferrable Disk Drive Warranty. _|n addition to the foregoing warranty, System Industries also pro- vides to Buyer the transferrable warranty, if any, provided to System Industries by the disk drive manufacturer.

Limitation of Warranty and Liability. The foregoing constitutes System Industries’ entire warranty, expressed, implied, and/or statutory (except as to title), and states the full extent of System Industries’ liability to Buyer or to any other party for any breach of such warranty and for damages, whether direct, special, incidental, or consequential. OTHER THAN AS EXPRESSLY PROVIDED IN THIS DOCUMENT, NO WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PUR- POSE, ARE MADE. NO EMPLOYEE, REPRESENTATIVE, OR AGENT OF SELLER HAS ANY AUTHORITY, EXPRESSED OR IMPLIED, TO ALTER OR TO SUPPLEMENT THE TERMS OF THIS WARRANTY.

PB9920-9001-02 iti

REVISION RECORD

REVISION | EO |

NUMBER NUMBER 01 4/15/83 Initial Release 1595 02 8/23/84 RPOX 9413

iv PB9920-9001-02

9900 CACHE BUS CPA USER’S GUIDE PREFACE

PREFACE

This manual contains sufficient information to enable the end user to install and operate the System In- dustries 9900 Cache Bus Computer Port Adapter (CPA). It should be read in conjunction with the 9900 Disk Controller User's Guide, PB9900-9001.

The information in this manual is presented in four sections and four appendices.

Section 1]

Section 2

Section 3

Appendix A

Appendix B

Appendix C

Appendix D

System Overview: Briefly describes the 9900 Disk Storage Subsystem (see the 9900 Disk Controller User's Guide for a detailed description of the 9900 Subsystem).

Physical Description: Describes the Cache Bus CPA.

Functional Description: Describes the functional operation of the Cache Bus CPA in the 9900 System.

Installation: Describes and illustrates the procedures required to install and cable the

Cache Bus CPA. RMOX Registers: Lists and explains all the RMOX registers.

RMOX Register Summary: Summarizes the hardware registers discussed in Appendix

RPOX Registers: Lists and explains all the RPOX registers.

RPOX Register Summary: Summarizes the RPOX hardware registers.

Other System Industries publications applicable to the 9900 Cache Bus CPA are as follows:

Publication Number Title

PB9400-9021 PB9400-9015 PB9900-9001 PB9901-9001

PB9920-9001-02

SIDiag User’s Guide

Overview Software Modifications User's Guide 9900 Disk Controller User’s Guide

Disk Drive User's Guide

CONTENTS 9900 CACHE BUS USER’S GUIDE

a :

TABLE OF CONTENTS Section Page 1 System Overview LGD System Capabilitvswstccotiehotadiew bad aka eau egue dl Yen eau ated 1-1 2 Physical Description 2.1 9900 Cache CPA Major Components ........... 00sec cece ce cee eee eens 2-1 3 Functional Description Sel UUNIBUS ConttolBOdrds: sics.dren sars.y aitelecs het a oe aud Aa RON Dados dene Cae a gees 3-1 Sed’ Control Registers. 4.4% owas dasha vdieo ae he Mace ceaeuhe eee lane eed 3-1] 3.3: Adaressdnd' ControliBoatd. o.0c.conr seid sad sedaogua Mate sdled of aw amen see 3-1 S4. ‘DOG BOOhGs 82.5505 ness ord ahd ee eae hana wale ea ented ek hae 3-] 3:0: Control Butter Board: itocc30, oy asc oe Od foley ti nas dae weouetd teed 3-2 4 Installation AAs NisvaliNsPOCHOn. 42 0. gickevin kaa Rae Guedes Sales a a heehee hws Bh uey 4-] Az “Switch and Jumper SenInGS<.cr04.c6 ence aw eee oases late hawk yetecucd se uees 4-1 #2 Ai NIBUS Address: freeride wad ok ee Es aul aan eee eek ee ee 4-] 4.27.2) Anteccupt Vector <2 2.0ccooi0% cheese tticatate heleasnwne eet vested eons 4-2 4.2.5: Bus Request Jumper 2i24.0ks ne Vow Gace ade xe ees tes eee e ete 4-3 a. 4:27:42) Bus Geaht JUMPElS 4 h2544s 2a eh ae 3d hee aR Caen eke s dues 4-5 ( 4.2.5 UNIBUS Control Board RM/RP Emulation Jumper ............-...-02005- 4-5 A-3. “Physical installation: seca pees So eG kt Gy ad ne eee es SRE ees 4-6 BM (COBING. id sdu ae enn acid Now te ea ee ateeale a yalamamlecen wha oniteecanerhs ealeteu se 4-7 AAA ‘CPAto Controller Cabling: oc. 22.000 dencexan ene kh dele sed eb aane ee wa 4-7 442° ‘Cabling Internalte the CPAs 65 .Ge ay awe ode tia saw sents Saeed key ee 4-7 AS “POWER REQUIFEMENIS cies. Gi:2elest ood oh e ek bined ia dns ead RE OWA ae doa EA REO SS 4-9 4.6:. Power source Check a5 in% ent teeta etna vew waa ete act Naat ite oo beead 4-9 Ady ‘Power FailtCireuh cs eaves eh tte ts aig 2S kek EX AN a we ea oe ease anes 4-9 Appendix A RMMOK Registers: acces ited os btu se Abe ee ew eee adekhahe seta ele ee ae acne A-1 B RMOX: Register SUMINGEY 3445 cee or ees ea P eee twee hed cree ede te hee B-1 C RPOX REG SHOES 5-3 ct ha sereth des Stas areas has teeelucs beh a dew are Wels Rae eer Nae oA AOE C-1 D RPOX Register: SumMOry he xcs oq a dlide aan na hie ellen ee Saws wd AE RAE EE CORRS D-1

vi PB9920-900 1-02

9900 CACHE BUS CPA USER'S GUIDE CONTENTS

TABLE OF CONTENTS

LIST OF ILLUSTRATIONS Figure

LIST OF TABLES Table

4-1 UNIBUS Secondary Address (776300) Switch Settings... ...... 0.0.0 ccc ccc eee cece eee eens 4-2 Interrupt Vector Secondary Address (150) Switch Settings .......0.. 00... cece cee eee eee a3. “BUS Request Um perso c:ked da teucatnth = wip als aati Geld had wa eee WEEN Ew hed NV ekanaeewla 4-4 BUS Grant Jumper Settings .............0.0 0000 c eee ee eee Sa ee eee eee eee ee eee 4-5 Slot Locations of the CPA Boards .................0000. Bit OS AAS he rd cere cet tise eer A-6e “f SV Reguigiot Slols o.oo sabe One Saent ana: ehceiald on Wee Oe Re Ree BEADS A- T+ -Eunction Code Control Bits: oo: tre nt-ven nde eee eels ede ealee ees ae ved ebicadateng ase cease A-2. Diwed ype Switch Settings. oc. ov bveees waves te bed oo ooo oo 5 FOS we eed eke as had wha hd ee Clr a -Funehion Gode Control Bits x. cc. ow eine Jan’ ato ulalind siete tent cruitan anaes aad aan: C2. Dive Tyce Switch Setings:. 1.42 i wa wieder nice oe oda CoU eed ets eed adnan Se boner ete

PB9920-9001-02

Page 4.4 4-6 4-8

vii/ viii

9900 CACHE BUS CPA USER’S GUIDE SYSTEM OVERVIEW

SECTION 1 SYSTEM OVERVIEW

1.1 System Capability

The System Industries 9900 Series Disk Storage Subsystem interfaces from one to eight Storage Module Drives (SMDs) or SMD interface compatible drives to Digital Equipment Corporation (DEC)™ com- puters.

PDP-11/70'™ on the internal cache bus.

D r neo ve tt

J> —- ot rai) Ne) Se) (om) (an) (@) re) = = —“s os a) “t wr Cc xe) Tw Q w

With ine Cache Bus C

DEC and PDP are trademarks of Digital Equipment Corporation

PB9920-9001-02 1-1/1-2

9900 CACHE BUS CPA USER'S GUIDE PHYSICAL DESCRIPTION

SECTION Z PHYSICAL DESCRIPTION

2.1 9900 Cache CPA Major Components

The 9900 Cache Bus Computer Port Adapter (CPA) consists of four printed circuit boards: e The UNIBUS control board (9400-61X4) measuring 9 x 16 inches (22.86 cm x 40.64 cm) e Address and control board (9400-61X1) measuring 9x 16 inches (22.86 cm x 40.64 cm)

ra AN

e Data board (9400-61X3) measuring 9 x 6 inches (22.86 cm x 30.68 cm) Control buffer board (9400-61X2) measuring 9x 12 inches (22.86 cm x 15.24 cm)

These boc

rds occupy a four-slot, RH70 controller dedicated area in the DEC PDP-11/70.

The CPA is connected to the controller by two flat 40-conductor cables.

RIATE mi

Part numbers for parts in the 9900 model family may vary in the second to the last digit (e.g., cache bus CPA address and control boards may have part numbers 9400-6101 or 9400-6111). If a specific part is required for an application, a specific part number will be given.

PB9920-9001-02 -9.1/9-2

9900 CACHE BUS CPA USER'S GUIDE FUNCTIONAL DESCRIPTION

SECTION 3 FUNCTIONAL DESCRIPTION

The Cache CPA provides the interface between the controller and the PDP-11/70 on both the internal cache bus for DMA transfers and the UNIBUS for register I/O and interrupt transactions. The CPA con- sists of the following:

e UNIBUS control board

pl eet et SN Ad Aaarvress and contro! board

e Data board e Control buffer board

The function of the CPA is to control the transfer of data between the coniroller and CPU memory.

3.1 UNIBUS Control Board

The UNIBUS control board inferfaces between the PDP-11/70 UNIBUS and the controller microprocessor bus by means of a RAM register file and discrete registers that both the CPU and microprocessor can access. The RAM register file contains eight sets of drive registers. There is one set of these registers for each drive. The file also contains additional control registers for I/O and DMA operations.

3.2 Control Registers

These registers contain drive status, command and address parameters, I/O and DMA transfer informa- tion, and error messages. Additional logic allows an interrupt to be requested with an interrupt vector address presented to the CPU. Interrupt enable (IE) is bit 6 of RMCS1. It is a control bit that can be set only under program control. It must be set for the CPA to generate an interrupt request to the CPU.

3.3 Address and Control! Board

The address and control board interfaces all the memory address and control lines between the cache bus and the UNIBUS control board. Its primary function is to control the buffer of the 32-bit data bus of the cache and the 16-bit data bus of the controller. This board is capable of doing 16-bit data transfers to the cache bus for start and finish addresses if necessary. A 22-bit address is sent from the UNIBUS control board with each data request. The board also sends back to the UNIBUS control board various status and error conditions. Actually there are 21 bits, since bit 0 is unused.

3.4 Data Board

The data board has two 16-bit buffers to interface the 32-bit cache bus and the 16-bit controller bus. When reading from memory, 32 bits of data are read and stored in the two buffers. The contents of the buffers are then sent to the controller. When writing to memory, 16 bits of data are sent from the con- troller and loaded into the first buffer. The next 16 bits are loaded into the second buffer and a write cycle is then initiated to the cache bus. The necessary actions are performed for 16-bit transfers to the cache bus if the start or finish address of the DMA transfer is an odd address.

FUNCTIONAL DESCRIPTION 9900 CACHE BUS USER'S GUIDE

3.5 Control! Buffer Board

The control buffer board routes control and error signals between the address and control board and the data board. This board obviates wiring changes in the backplane of the PDP-11/70 CPU.

3-2 PB9920-9001-01

9900 CACHE BUS CPA USER'S GUIDE

SECTION 4 INSTALLATION

INSTALLATION

This section contains the information required to install the 9900 Cache Bus CPA in a PDP-11/70 and to cable the CPA to the controller. The section contains the following information:

Switch and jumper settings

Physical installation of the CPA Cabling information and procedures Power requirements

Power source check

Power faii circuit

WARNING

Care should be exercised during the installation process to prevent damage fo the system or personal injury. !t is necessary to power down all or part of the computer system and to disconnect power cords from the AC power source to attach the CPA.

4.1 Visual Inspection

Before attempting to install this device, perform a visual inspection to verify the following:

All components are undamaged, in place and secure. Connector pins are not bent or otherwise damaged.

Cables are not kinked or cut.

4.2 Switch and Jumper Settings

Two switch settings and three jumper settings must be checked and, if necessary, reset for the CPA to operate correctly with the controller. The following paragraphs describe the switch and jumper settings necessary to configure the CPA.

4.2.1 UNIBUS Address

Set the UNIBUS address switch SW2 located at grid position 3E on the UNIBUS control board (9400-61X4). Refer to Table 4-1 for the switch settings and to Figure 4-1 for location of the switch. The switch settings in Table 4-1 represent the value of the secondary address (776300).

4-]

INSTALLATION 9900 CACHE BUS CPA USER'S GUIDE

With SW2 set as indicated in Table 4-1, toggling the STD/ALT switch on the UNIBUS control board (located at grid position 5R) to the ‘STD’ position will select the value of the primary address (776700), and toggling it to the ‘ALT’ position will select the value of the secondary address (776300).

Nonstandard UNIBUS addresses may be selected by setting the appropriate UNIBUS address switches with the STD/ALT switch set to the ‘ALT’ position. A switch in the OFF position produces a logical ] on the corresponding UNIBUS address line.

Table 4-1. UNIBUS Secondary Address (776300) Switch Settings

UNIBUS c ADDRESS LINE

SWITCH NUMBER | SWITCH SETTING

NC = No connection

NOTE

If the user has selected a UNIBUS address other than the primary or secondary address (i.e., has set switch SW2 differently than indicated in Table 4-1), the ‘ALT’ mode of the STD/ALT toggle switch must be us- ed. It will select the address set by switch SW2. The ‘STD’ mode must not be used.

4.2.2 Interrupt Vector

Set the interrupt vector switch SW1 located at grid position 3D on the UNIBUS control board. Refer to Table 4-2 for the switch settings and to Figure 4-1 for the board location of the switch. The switch set- tings in Table 4-2 represent the value of the secondary interrupt vector (150g).

With SW1 set as in Table 4-2, toggling the STD/ALT switch (located at grid position 5R) to the ‘STD’ posi- tion will select the primary interrupt vector (254g), and toggling it to the ‘ALT’ position will select the secondary interrupt vector (150s).

Nonstandard interrupt vectors can be selected by setting the appropriate interrupt vector switches with

the STD/ALT switch set to the ‘ALT’ position. A switch in the OFF position produces a logical 1 on the corresponding UNIBUS address line.

4-2 PB9920-9001-02

9900 CACHE BUS CPA USER'S GUIDE

Table 4-2. Interrupt Vector Secondary Address (150) Switch Settings

UNIBUS ADDRESS LINE SWITCH NUMBER SWITCH SETTING

a ae ee ee ee 3 4 OFF | 4 + = 4 | 5 ' ON 5 6 | OFF a l 6 | 7 | OFF = —t | 7 8 ON 0 = ON

1 = OFF NC = No Connection

NOTE

If the user has selected an interrupt vector address other than the primary or secondary address (i.e., has set switch SW1 differently than indicated in Table 4-1), the ‘ALT’ mode of the STD/ALT toggle switch must be used. It will select the address set by switch SW1. The ‘STD’ mode must not be used.

4.2.3 Bus Request Jumper

INSTALLATION

Verify that the bus request jumper W3 (in etch) located on the UNIBUS control board, is wired as in Figure 4-1. This configuration produces normal BR5 priority. Refer to Table 4-3 for additional bus

request settings and to Figure 4-1 for the board location of the jumper.

Table 4-3. Bus Request Jumpers

BUS REQUEST PRIORITY LEVEL

JUMPER CONFIGURATION

W383 connected to E

W3 connected to F

4

BR6 W3 connected to G al

BR7 W3 connected to H

4-3

INSTALLATION

9900 CACHE BUS CPA USER'S GUIDE

FS Seah pe as Sey | ae i een ee | SEE SEE SEE DETAIL A DETAIL B DETAIL C & D 3D SWI ry 2 3 4 5 6 7 8 | mw CITT | DETAIL C 1 & 8 oO 0 vt7 0 4 are) ere olo o O WI Ww2 @) ©) 4 5

BUS GRANT JUMPERS

Figure 4-1.

4-4

Lara ens, anal

a: a | | WA = Sess | | | rn | a | SEE DETAIL E 3E | SW 2 ane ee ae DETAIL A Ce et Pe DETAIL B iNTERRUPT VECTOR ON UNIBUS ADDRESS SWITCH SWITCH OFF DETAIL D DETAIL E E ALT --F7O 5 eee a: we (T2 SID ° H

BUS REQUEST JUMPERS

UNIBUS Control! Board

PB9920-9001-01

9900 CACHE BUS CPA USER'S GUIDE INSTALLATION

4.2.4 Bus Grant Jumpers

Verify that the bus grant jumpers W1, W2, A, B, C, and D, (these jumpers are etched) located on the UNIBUS Control board, are wired as in Figure 4-1. This jumper configuration produces normal BGS priority. Refer to Table 4-4 for additional bus grant settings.

Table 4-4. Bus Grant Jumper Settings

BUS GRANT PRIORITY LEVEL

JUMPER CONFIGURATION

W1 connected to 1

W2 connected to 8

A - out B,C,D - in

W1 connected to 2 W2 connected to 7 | B - out A,C,D - in

BG5

W1 connected to 3 BG6 W2 connected to 6 C - out A,B,D - in

W1 connected to 4 BG7 W2 connected to 5 D - out A,B,C - in

NOTE

The bus grant and bus request jumpers must be set at the same priority level.

4.2.5 UNIBUS Control Board RM/RP Emulation Jumper

Verify that jumper W4, located on the UNIBUS control board, is removed for RM emulation. For RP emulation the jumper should be installed. The jumper location is shown in Figure 4-1.

PB9920-9001-02 4-5

INSTALLATION 9900 CACHE BUS CPA USER'S GUIDE

4.3 Physical Installation

The four boards comprising the CPA are placed in one of the four-slot areas in the PDP-11/70 normally allocated for RH70 controllers (see Figure 4-2). Remove the bus grant continuity card in the UNIBUS control board slot before plugging in the UNIBUS control board. Table 4-5 lists the individual slot loca- tions for the CPA boards in each of the four available areas.

Table 4-5. Slot Locations of the CPA Boards

RH70 9400-61 X4 9400-61 X1 9400-61 X2 9400-61 X3 DEDICATED SLOT SLOT SLOT SLOT LOCATIONS LOCATIONS LOCATIONS LOCATIONS

9400-61 X1

9400-6 1X2 i 9400-61X4 a”

9400-61X3

ne

CECE | Het

| 44 | 43 42] 41 | 40 | 39 | 38 | 37 | 36 | 35 34 | 33 | 32/31 | 30 | 29 | 28 | 27 | 26 | 25 | 24

SPC SPC SPC SPC CONTROLLER CONTROLLER CONTROLLER | CONTROLLER E D C B D Cc B A

Figure 4-2. Cache Bus CPA Locations in the PDP-11/70

4-6 PB9920-9001-02

9900 CACHE BUS CPA USER'S GUIDE INSTALLATION

4.4 Cabling The following paragraphs detail the cabling from CPA to controller and the internal cabling of the CPA.

4.4.1 CPA to Controller Cabling

The controller is connected to the CPA by two cables. Both are 40-conductor ribbon cables originating at the computer interface (Cl) board (9400-60X7) located in the controller enclosure (See Figure 4-3).

Th. fact enbl. [OANN_FNNO -- 191 aytee ele fn pan enctoe ee te connac The first cable \74UU-7 008 or 9400-70 13) extends from connector J rdt tor J]

on the UNIBUS control board (9400-61X4)

The second cable (9400-7217 or 9400-7218) provides a three-way interface, extending from connector J2 on the Cl board to connector J1 on the data board (9400-61X3) and to connector J2 on the UNIBUS control board (9400-61X4).

4.4.2 Cabling Internal to the CPA

A 40-conductor ribbon cable (9400-7216) extends from connector J3 on the UNIBUS control board (9400-61X4) to connector J1 on the address and control board (9400-61X1). Refer to Figure 4-3.

PB9920-9001-02 4-7

INSTALLATION 9900 CACHE BUS CPA USER'S GUIDE

FROM J1 ON THE: C1 BOARD 9400-6007

FROM 9900 CONTROLLER

FROM J2 ON Cl BOARD 9400-6007

CACHE ADDRESS AND CONTROL CABLE

bd re [a‘4 ed z 30 —W $2 85 aD a x oO > ca 9400-6111 3 < ADDRESS AND G< oO

CONTROL BOARD

9400-61 al

CONTROL BUFFER BOARD

Figure 4-3. Cache Bus CPA Cabling

4-8 PB9920-9001-02

9900 CACHE BUS CPA USER’S GUIDE INSTALLATION

4.5 Power Requirements The following voltage is required to operate the Cache Bus CPA: +5VDC @ 7.5 Amps Maximum

It is obtained from the PDP-11/70 backplane.

4.6 Power Source Check

To ensure reliable operation of the CPA, the PDP-11/70 backplane voltage at each CPA printed circuit board must be checked, and, if necessary, adjusted after the boards have been installed. There are three +5VDC power supply regulators that supply the RH70 slots (see Table 4-6). With the boards in place, the + 5VDC on the backplane of each slot, measured at pin FV1, must be within the range 5.00V to 5.10V.

If any of the regulators requires adjustment or replacement, contact the DEC field service represen- tative for assistance.

Table 4-6. +5V Regulator Slots

+5V REGULATOR | RH70 SLOTS SUPPLIED

24 25 26 27 28

29 30 31 32 33 34 35 36 37 38 39

4.7 Power Fail Circuit

Certain CPAs have a CPA power fail circuit which works in conjunction with power-fail circuitry on the 9400-6017 or 9400-6027 computer interface (Cl) board to prevent spurious commands from being recognized by the controller when a CPA power failure occurs. This feature was introduced on Cache Bus CPA boards with part number 9400-6104 and a date code of 129 or later. Further revisions of this board, e.g., 9400-6114, also have this circuit.

Boards with part numbers 9400-6104 and a date code earlier than 129 do not have this feature. For

these boards it is necessary to disable the Cl board power fail circuit by setting a switch. Refer to the

9900 Disk Controller User's Guide, PB9900-9001, for details of this procedure.

PB9920-9001-02 4-9/4-10

9900 CACHE BUS CPA USER'S GUIDE RMOX REGISTERS

APPENDIX A RMOX REGISTERS

RMO3/05 Registers Registers are referred to by their name and UNIBUS primary address.

Control and Status #1 Register (RMCS1) (776700)

RMCS1 can be read or written by program control and is used to store the current disk command func- tion code and operational status of the 9900 Disk Controller.

Bit Name Function

15 Special Condition (SC) Set when TRE (bit 14) or any drive’s ATA bit (RMAS bits 07-00) is set. Cleared by clearing the TRE or ATA conditions.

14 Transfer Error (TRE) Set when one or more of RMCS2 bits 15-08 (DLT, WCE,

UPE, NED, NEM, PGE, MXF, MPDE) are set, or when a

drive error occurs during a data transfer.

Cleared by UNIBUS INIT, controller clear, by loading a data transfer command with GO (bit 00) set, or by writing a 1 into this bit causing an error clear.

13” MASSBUS Control Bus Parity Set to 0 by the controller. Error (MCPE) | 12 Not Used Set to 0 by the controller. 11* Drive Available (DVA) Always read as 1. 10* Port Select (PSEL) Used to direct a data transfer to a Cl port other than the

one corresponding to this CPA. When a data transfer com- mand is initiated with PSEL set to 1, the data transfer will be directed to or from the Cl port specified by bits 01-00 of RMOF. Note that the CPU connected to the alternate CPA must have previously loaded its RMBA and RMWC.

Cleared by UNIBUS INIT, controller clear or by writing a 0 to this bit.

09-08 UNIBUS Address Extension Upper extension bits of the RMBA register. Bits (A17-A18) Cleared by UNIBUS INIT, controller clear, or by writing 0's in these bits.

07 Ready (RDY) Normally RDY = 1. During data transfers, RDY = 0. When a data transfer command code (513-73) is written into RMCS1, RDY is reset. At the termination of the data transfer, RDY is set.

*A register bit followed by an asterisk(*) indicates a bit whose function differs from DEC definitions. MASSBUS is a trademark of Digital Equipment Corporation

PB9920-9001-02 A-1

RMOX REGISTERS 9900 CACHE BUS CPA USER'S GUIDE

RMCS1 (Continued)

Bit Name Function

06 Interrupt Enable (IE) IE is a control bit that can be set only under program con- trol. Setting IE enables an interrupt to occur when the following conditions are satisfied:

1. Upon termination of a data transfer if JE is set when RDY becomes asserted.

2. If SC (bit 15), IE, and RDY (bit 07) are all asserted.

3. Ifthe program writes ones into IE and RDY at the same time.

When a 0 is written into IE by the program, any pending in- terrupts are disabled.

Cleared by UNIBUS INIT, controller clear or automatically cleared when an interrupt is recognized by the CPU.

05-00 F4-FO and GO Bit F4-FO and the GO bit (00) function (command) code control bits (Table A-1):

Table A-1. Function Code Control Bits ; F4 F3 F2 FI FO GO Octal :

0 0 01 No operation 05 | Seek 07 Recalibrate | 11 | Drive clear | 13 Release | 15 Offset

17 Return to centerline 21 Read-in-preset

23 Pack acknowledge 25 | System reserve (extended mode only)*, 27 | System release (extended mode only)*!

] 1 1 ] ] 1 1 1 1 1 ] 1 31 Search* ] ] ] ] 1 ] ] 1 1 ]

51 Write check data 53 Write check header and data 55 | Call micro (extended mode only)* 61 Write data

63 | Write header and data

65 | Write micro (extended mode only)* 67 | Autoformat (extended mode only)* 7 Read data

73 Read header and data

75 Read micro (extended mode only)*

ee ooo RooloRoRo—oRo—=) —]=] |] 4s 4 OO00-]-=]-+-=0COTDO0000 —“=-=-9Q000]-=-=+-+-0000-=-=—-=000 “O0O0-—-0C00+-000-—-00-=-00-—0 o-O-0O-00—-00-0—-0—-0—-0—-0

*S] Function

GO (bit 00) must be set to cause the controller to respond to a command. GO is reset by the controller after command execution.

Cleared by UNIBUS INIT or controller clear. A-2 PB9920-9001-02

9900 CACHE BUS CPA USER’S GUIDE : RMOX REGISTERS

Word Count Register (RMWC) (776702)

RMWC is loaded by the program with the two's complement of the number of words to be transferred. A maximum of 65,536 words can be transferred at one time.

Bit Name Function 15-00 Word Count (WC) Set by the program to specify the number of words to be

transferred (two's complement form).

RMWC is updated by the controller at the completion of the DMA transfer.

Cleared by writing zeros into these bits.

UNIBUS Address Register (RMBA) (776704)

RMBA is used to address the memory location in which a transfer is to take place. The RMBA forms the lower 16 bits of the address that combine with bits 05-00 of the Bus Address Extension Register {(RMBAE) to create the 21-bit memory address (A17 and A16, RMCS1 bit 09 and 08, are also UNIBUS address extension bits and provide another means of reading or writing bits 17 and 16 of the extended UNIBUS address). The register is loaded with the starting memory address by the program. Each time a DMA transfer is made, the register is incremented by 2. If BAI (bus address increment inhibit, RMCS2 bit 03) is set, the incrementing of the register is inhibited and all transfers take place to or from the starting memory address.

Bit Name Function 15-01 UNIBUS Address (BA) Loaded by the program to specify the memory address of a transfer.

RMBA is incremented by 2 after each transfer of a word to or from memory.

Cleared by UNIBUS INIT, or by controller clear.

00 Not Used Always read as 0.

PB9920-9001-02 A-3

RMOX REGISTERS 9900 CACHE BUS CPA USER'S GUIDE

Desired Sector/Track Address Register (RMDA) (776706)

RMDA register is used to address the sector and track on the disk to or from which a transfer is desired. RMDA is associated with the drive whose unit number appears in bits 02-00 of the Control and Status 2 register (RMCS2). Before a transfer, RMDA is loaded by the program with the address of the first block to be transferred. At the end of a transfer, RMDA contains the address of the block following the last block of the transfer.

The RMDA contains a 6-bit sector address field providing for 48 sectors per track (SI 9751 only). The register also contains a 6-bit track address field providing for up to 64 data tracks per cylinder.

TA32 | TAI6 | TAB SA32 | SAI6 } SAB Bit Name Function 15-14* = Not Used Set to 0 by the controller.

13-08* = Track Address (TA32-TA1) Set by the program to specify the track on which a transfer is to start.

Updated by the controller at the end of the transfer. Cleared by UNIBUS INIT. .

f 07-05 Not Used Set to 0 by the controller. ¢

05-00* Sector Address (SA32-SA1) Set by the program to specify the sector on which a transfer is to start. Bit 5 is used if there is an SI 9751 in the system. Updated by the controller at the end of the transfer.

Cleared by UNIBUS INIT.

*Function differs from DEC definition.

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9900 CACHE BUS CPA USER’S GUIDE

RMOX REGISTERS

Control and Status #2 Register (RMCS2) (776710)

RMCS2 indicates the status of the controller and contains the drive unit number. The unit number specified in bits 02-00 of this register indicates which of the possible 8 logical drives is selected.

15 14 13 12 1] 10 09

08 07 06 05 04 03 02

jo | wee | ure | neo | nem | ect | mur | more Gedlsecle aa an ere ee

Bit Name

15* Data Late (DLT)

14 Write Check Error (WCE) 13 UNIBUS Parity Error (UPE) 12 Nonexistent Drive (NED)

1] Nonexistent Memory (NEM)

*Function differs from DEC definition. PB9920-9001-02

Function Set to 0 by the coniroller.

Set when the controller is performing a write-check opera- tion and a word on the disk does not match the correspon- ding word in memory.

WCE causes TRE (RMCS1 bit 14) to be set. If a mismatch is detected during a write-check command execution, the transfer terminates and WCE is set. The memory address

displayed i in RMBA (and RMBAE bits 05-00) is the address of the word following the one that did not match {if BAI, bit

03, is not set). The mismatched data word from the disk is displayed in RMDB.

Cleared by UNIBUS INIT, controller clear, error clear, or loading a data transfer command with GO (RMCS1 bit 00) set.

Set if any of RMCS3 bits 13, 14, or 15 (DPEE, DPEO, or APE) are set while the controller is performing a data transfer command.

UPE sets TRE (RMCS1 bit 14). RMBA contains the address +2 of the memory location with the parity error.

Cleared by UNIBUS INIT, controller clear, error clear, or by loading a data transfer command with GO (RMCS1 bit 00) set.

Set when the program attempts a command on a drive that does not exist or is powered down.

NED sets TRE (RMCS1 bit 14). Cleared by UNIBUS INIT, controller clear, error clear, or

by loading a data transfer command with GO (RMCS1 bit 00) set.

Set when the controller is performing a DMA transfer and the memory address specified in RMBA is nonexistent (does not respond to MSYN within 10 microseconds).

NEM sets TRE (RMCS1 bit 14). RMBA contains the address

+2 of the memory location causing the error.

Cleared by UNIBUS INIT, controller clear, error clear, or by loading a data transfer command with GO (RMCS1 bit 00) set.

A-5

RMOX REGISTERS

RMCS82 (Continued)

Bit 10

09*

08*

07 06*

05

04*

03

02-00

Name Program Error (PGE)

Missed Transfer (MXF)

MASSBUS Data Bus Parity Error (MDPE)

Oi'put Ready (OR) Input Ready (IR)

Controller Clear (CLR)

Parity Test (PAT)

UNIBUS Address Incre- ment inhibit (BAI)

Unit Select (U2-U0)

*Function differs from DEC definition.

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9900 CACHE BUS CPA USER'S GUIDE

Function Set when the program attempts to initiate a data transfer operation while the controller is currently performing one.

PGE sets TRE (RMCS1 bit 14).

Cleared by UNIBUS INIT, controller clear, or error clear. Set if the controller fails to detect an end of header or end of sector, or the data buffer fails to empty during a data transfer. MFX sets TRE (RMCS1 bit 14).

Cleared by UNIBUS INIT, controller clear, error clear, or by loading a data transfer command with GO (RMCS1 bit 00) set.

Set to 0 by the controller.

Set by the controller to indicate a word is in RMDB. Set to 1 by the controller.

When a 1 is written into this bit, the controller and all drives are initialized. Always read as 0.

PAT has no effect on controller operation.

Cleared by UNIBUS INIT or controler clear.

When BAI is set, the controller will not increment the RMBA register during a data transfer. BAI bit cannot be modified

while the controller is doing a data transfer (RDY, RMCS1 bit 07, negated).

When set during a data transfer, all data words are read from or written into the same memory location.

Cleared by UNIBUS INIT or controller clear.

U2-U0 bits are written by the program to select a drive.

The unit select bits can be changed by the program during data transfer operations without interfering with the transfer.

Cleared by UNIBUS INIT or controller clear.

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9900 CACHE BUS CPA USER'S GUIDE RMOX REGISTERS

Drive Status Register (RMDS) (776712)

RMDS contains status indicators for the selected drive. The status indicators displayed are those of the drive that is specified by the unit select bits (02-00) of the RMCS2.

15 14 13 12 1] 10 09 08 07 06 05 04 03 02 01 00

Rit Name Function

15 Attention Active (ATA) An attention condition from a drive will set the ATA bit and the corresponding summary bit in RMAS.

ATA is cleared by UNIBUS INIT, controller clear, drive clear, loading a command with GO bit (RMCS1 bit 00)set or, if no error conditions exist, by writing a 1 into the RMAS register bit corresponding to the drive's unit number.

An attention condition is caused by:

1. Completion of seek, search, recalibrate, offset,

to centerline.

2. MOL (bit 12) changing state.

or return

14 Error (ERR) Set when one or more error bits in the error registers (RMER1 or RMER2) for a selected drive is set, indicating a drive error has occurred.

Cleared by UNIBUS INIT, controller clear, drive clear, or by writing zeros into the set error bit(s) in the error registers.

13* Positioning In Progress (PIP) | Always read as 0. 12 Medium On-line (MOL) Set for the drive upon the successful completion of the start- up cycle.

This bit is set when the unit ready line from the drive is asserted (indicating that the drive is up to speed, the heads are positioned over the recording tracks, and no fault con- dition exists within the drive), and is reset when the unit ready line is deasserted.

Cleared when the drive is spun down or switched off.

1] Write Lock (WRL) Set when the write protected line from the drive is asserted (as enabled by a switch located on the drive), indicating that the drive will not accept write commands. A write com-

mand issued on a write-locked drive will cause WLE

(RMER1 bit 11) to be set.

*Function differs from DEC definition.

PB9920-9001-02 A-7

RMOX REGISTERS

RMDS (Continued)

Bit 10

09* 08*

07

06

05-01

00

Name .

Last Sector Transferred (LST)

Programmable (PGM) Drive Present (DPR)

Drive Ready (DRY)

Vc,ume Valid (VV)

Not Used

Offset Mode (OM)

*Function differs from DEC definition.

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9900 CACHE BUS CPA USER'S GUIDE

Function Set when last addressable sector on the disk pack has been read or written.

Always read as 0. Set if the drive is powered up. Set at the completion of every command, data handling or

mechanical motion.

If this bit is reset, the program must not issue another com- mand to this drive. When set, this bit indicates the readiness of the drive to accept a new command.

DRY is the complement of GO (RMCS1 bit 00) except when the drive is nonexistent; then DRY is reset.

Cleared at the initiation of a command.

Set by the pack acknowledge or read-in preset command.

When reset, VV bit indicates that the drive has been spun down and then up, and that a disk pack may have been changed.

Cleared whenever drive spins up (i.e., when MOL, bit 12, becomes asserted) or when the CPU powers up.

Always read as 0.

Set when offset command is issued to a drive. When set, and a read command is received, the offset is performed prior to the execution of the read.

Reset by any of the following actions: Power-up

Mid-transfer seek

Write data or write header and data Return to centerline

Pee i a

Recalibrate

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9900 CACHE BUS CPA USER'S GUIDE RMOX REGISTERS

Error Register #1 (RMER1) (776714)

RMER1 contains the error status indicators for the drive whose unit number appears in bits 02-00 of RMCS2. The logical OR of all the error bits in the RMER1 and RMER2 registers is